The present invention relates to an emulation system and an information processing device.
An interface between CPU 900 and input devices including keyboard 950 and mouse 960 in a conventional personal computer (PC) which is an information processing device is shown in FIG. 1. Between the CPU 900 and the keyboard and mouse (950, 960), there exists an input/output controller which comprises a chip (e.g., the Intel 8042) or compatible chip of 8042 and its peripheral circuits. In such PC, data will not be transmitted directly between the CPU 900 and the keyboard and mouse (950, 960). Instead, the 8042 (or firmware operating on the 8042) performs the control of the keyboard and mouse (950, 960) and the reception/transmission of data. The firmware has been stored in ROM within the 8042. In FIG. 1, other reference numerals 910, 912 and 914 denote an address decoder, interrupt controller and reset circuit, respectively.
FIG. 2 is an internal block diagram showing the details of the input/output controller. The 8042 comprises a processor 920, an output buffer 922, an input buffer 924, a status register 926, port registers (I/O ports) 928, 930 and others.
The reception/transmission of data in this arrangement of the prior art will now be described in brief.
1. When data is transmitted from BIOS (which is an input/output handler) to the 8042:
(1) BIOS waits until xe2x80x9cInput Buffer Fullxe2x80x9d, that is a flag held by the status register 926, becomes 0; and
(2) BIOS writes data on the input buffer (port 60h or 64h) if xe2x80x9cInput Buffer Fullxe2x80x9d becomes 0.
2. When BIOS receives data from the 8042 without interrupt:
(1) BIOS waits until a flag xe2x80x9cOutput Buffer Fullxe2x80x9d of the status register 926 becomes 1; and
(2) BIOS reads data from the output buffer 922 (port 60h) if xe2x80x9cOutput Buffer Fullxe2x80x9d becomes 1.
3. When BIOS receives data from the 8042 with interrupt:
(1) If IRQ1 or IRQ12 occurs, the control is shifted to its interrupt handler (which is one of input/output handlers);
(2) The interrupt handler reads data from the output buffer 922 (port 60h);
(3) The interrupt handler executes a predetermined process such as storing the read data in a given memory area; and
(4) The control is returned from the interrupt handler.
However, the prior art raised problems as follows.
(A) The necessity of the 8042 leads to an increased cost.
(B) The 8042 requires an additional area on which it is to be mounted.
(C) The 8042 requires an executable firmware. In other words, the system requires two types of programming languages for both CPU and the 8042.
(D) Since a firmware is normally stored in the mask ROM within the 8042, time and cost are required to change the firmware for correcting any trouble or for adding any additional function.
One emulation technique relating to an input/output controller such as the 8042 is known, for example, from Japanese Patent Application Laid-Open No. 7-334373. PC9821 produced by NEC (which uses a second architecture) or PC 486 produced by Seiko Epson Co. uses the Intel 8251A as an input-output controller for keyboard or others. An object of this prior art is to use the 8042 used in PC/AT computer (which uses a first architecture) produced by IBM as an input-output controller for PC9821 or the like, instead of the 8251A.
The 8042 suiting to the PC/AT machines of the first architecture that dominates large shares of the hardware and software markets can relatively early be developed for advanced machines and more easily be available, than the 8251A suiting to the PC9821 machines of the second architecture. If the 8042 is used in the PC9821 machines, therefore, the developing and manufacturing costs thereof can be reduced. Thus, the aforementioned prior art realized various emulation techniques for properly actuating the 8042 in the PC9821 machines in which the software for the 8251A operates.
However, this prior art cannot still overcome the above problems (A)-(D). More particularly, this prior art utilizes the hardware resource of the 8042 to perform an emulation. Thus, it still requires the 8042, resulting in increase of the manufacturing cost. Furthermore, the prior art also requires an additional area on which the 8042 is to be mounted and two types of programming languages for CPU and the 8042. In addition, time and cost are required to modify the firmware.
In view of the above problems of the prior art, an object of the present invention is to provide an emulation system and information processing device which can realize an emulation for the input/output controller without utilization of the hardware resource of the input/output controller
To this end, the present invention provides an emulation system for emulating an input/output controller which controls an input/output device without the hardware resource of the input/output controller. This emulation system comprises: a reception/transmission circuit for receiving data from and transmitting data to the input/output device; at least one of an output buffer for temporarily storing data from the input/output device, an input buffer for temporarily storing data from a given input/output handler, a status register for storing given status data, and a port register for transmitting given data to an external means; an interrupt generating circuit for generating a first interrupt for a central control means; and an emulation handler which is activated by the first interrupt for executing a given emulation.
By providing the reception/transmission circuit, the reception/transmission of data from and to the input/output devices such as mouse, keyboard and the like can be performed. The output buffer can temporarily store the data from the input/output devices while the input buffer can temporarily store the data from the input/output handler such as BIOS or interrupt handler. The status register can transmit the given status data to the input/output handler and the port register can transmit various data to the external. When the emulation handler is activated by the first interrupt from the interrupt generating circuit, the emulation handler can execute various processes such as the mutual delivery of data between the reception/transmission circuit and the output buffer or between the input/output handler and the input buffer, the control of the reception/transmission circuit, the writing of data into the status register or port register and so on. Therefore, the input/output controller can be emulated without utilization of the hardware resource thereof. AS a result, the cost of manufacturing the information processing device can be reduced, and firmware languages required to operate the information processing device can be unified. In addition this information processing device can easily accommodate a new input/output device.
The interrupt generating circuit may generate the first interrupt when reception of data from the input/output device is completed by the reception/transmission circuit, and the emulation handler activated by this first interrupt may read data from the reception/transmission circuit and write the data or converted data into the output buffer. In this way, the emulation of data transfer from the input/output device to the output buffer can be accomplished while maintaining the compatibility with the case wherein the input/output controller is used.
The reception/transmission circuit may include a circuit for converting serial data send by the input/output device into parallel data, and the interrupt generating circuit may generate the first interrupt when conversion of serial data into parallel data is completed by the reception/transmission circuit. The reception of data from the input/output device is thus possible without monitoring transfer clocks which are used in the reception of data from the input/output device. This reduces a burden in processing.
The emulation handler may terminate emulation without writing data into the output buffer when the input/output handler has not read data in the output buffer. Any later received data can be thus prevented from not being delivered to the input/output handler. This can avoid any loss of received data.
After the reception/transmission circuit completes reception of data from the input/output device, the emulation handler may inhibit the input/output device from transmitting subsequent data until the emulation handler delivers received data to the input/output handler. In this way, the data from the input/output device can be prevented from being repeatedly received. This enables proper data reception.
The emulation handler may set an output buffer data presence flag in the status register after writing data into the output buffer, and then terminate emulation. The presence of data in the output buffer can be thus transmitted to the input/output handler. Therefore, the input/output handler ran read the output buffer after being enabled to start processing.
The output buffer data presence flag may be reset when the input/output handler reads the output buffer after confirming that the output buffer data presence flag has been set. The output buffer data presence flag can be reset by a given circuit when the output buffer is read by the input/output handler. Therefore, it is not required to activate the emulation handler only for resetting the output buffer data presence flag. This reduces a burden in processing. It is further desirable that the emulation handler is again activated if there is any other necessary processing such as cancel of inhibition of data transfer of the input/output device when the output buffer is read by the input/output handler.
The interrupt generating circuit may generate the first interrupt again when the input/output handler reads the output buffer after confirming that the output buffer data presence flag has been set, and the emulation handler activated again by the first interrupt may execute a given processing corresponding to a factor of the first interrupt. In this way, the emulation handler can be used to accomplish a given processing such as delivery of data from the output buffer to the input/output handler, reset of the output buffer data presence flag in the status register, cancel of inhibition of data transfer of the input/output device.
The interrupt generating circuit may generate the first interrupt when the input/output handler writes data into the input buffer, and the emulation handler activated by this first interrupt may receive data writter into the input buffer and reset an input buffer data presence flag in the status resister, the input buffer data presence flag having been previously set by the writing operation of the input/output handler. In this way, the emulation of receiving data from the input/output handler can be realized while maintaining the compatibility with the case where the input/output controller is used.
In this case, data written into the input buffer is intended to be data in a broad sense, including data in a narrow sense, commands or the like. In addition to data to be transmitted to the input/output device, various types of data such as data to be written into the port register can be send by the input/output handler. It is further desirable that a given circuit is used to set the input buffer data presence flag when the input/output handler writes into the input buffer.
The emulation handler may write received data into the reception/transmission circuit. The data can be transmitted to the input/output device without the input/output handler knowing the intervention of emulation.
The reception/transmission circuit may include a circuit for converting parallel data written by the emulation handler into serial data. In this way, data can be transmitted to the input/output device without monitoring transfer clocks which are used in the transmission of data to the input/output device. This reduces a burden in processing.
When data from the input/output handler is a command with a parameter, the emulation handler may transmit the command to the input/output device through the input buffer and the reception/transmission circuit, and then enable the input/output handler to start processing; when the input/output handler starts processing and writes the parameter into the input buffer, the interrupt generating circuit may generate the first interrupt again; and the emulation handler activated again by the first interrupt may transmit the parameter to the input/output device through the input and output buffers and the reception/transmission circuit. Even if data from the input/output handler is a command with a parameters the command or parameter can be transmitted to the input/output device while maintaining the compatibility with the case where the input/output controller is utilized.
The present invention further provides an emulation system for emulating an input/output controller which controls input/output devices. This emulation system comprises: an Universal Serial Bus (USB) controller for receiving and transmitting data from and to a plurality of input/output devices connected to USB; at least one of an output buffer for temporarily storing data from the input/output devices, an input buffer for temporarily storing data from a given input/output handler, a status register for storing given status data, and a port register for transmitting given data to an external means; an interrupt generating circuit for generating a first interrupt for a central control means; and an emulation handler which is activated by the first interrupt for executing a given emulation. The present invention further provides an emulation system for emulating an input/output controller which controls input/output devices. This emulation system comprises: an IEEE1394 controller for receiving and transmitting data from and to a plurality of input/output devices connected to a bus meeting the IEEE1394 standard; at least one of an output buffer for temporarily storing data from the input/output devices, an input buffer for temporarily storing data from a given input/output handler, a status register for storing given status data, and a port register for transmitting given data to an external means; an interrupt generating circuit for generating a first interrupt for a central control means; and an emulation handler which is activated by the first interrupt for executing a given emulation.
According to the present invention, USB or the IEEE1394 interface, which realizes a high-speed serial data transfer, Plag and Play, and connection with a number of input/output devices without modification of application program or operating system, can be utilized. Furthermore, the compatibility can highly be improved in comparison with the case where the emulation is performed by device drivers.
The USB controller may generate a second interrupt for the central control means when receiving data from the input/output devices, and an interrupt handler activated by the second interrupt may enable the emulation handler to start processing only when the received data is send by a particular input/output device. The IEEE1394 controller also may generate a second interrupt for the central control means when receiving data from the input/output devices; and an interrupt handler activated by the second interrupt may enable the emulation handler to start processing only when the received data is send by a particular input/output device. In this way, only when data is transmitted by a particular input/output device, that is a keyboard or mouse for example, the emulation can be performed. Therefore, the emulation system can appropriately accommodate even when various other input/output devices are connected to USB or the IEEE1394 bus.
The present invention further provides an emulation system for emulating an input/output controller which controls an input/output device without the hardware resource of the input/output controller. This emulation system comprises: at least one of an output buffer for temporarily storing data from the input/output device, an input buffer for temporarily storing data from a given input/output handler, a status register for storing given status data, and a port register for transmitting given data to an external means; an interrupt generating circuit for generating a first interrupt for a central control means; and an emulation handler which is activated by the first interrupt for executing a given emulation; wherein the emulation handler emulates processings of at least one of a processor in the input/output controller and a processor in the input/output device.
According to the present invention, processings of one of the processors in the input/output controller and input/output device can be emulated. The prior art required three processors, including a processor in the main unit of an information processing device, if both the input/output controller and input/output device have processors. However, the present invention can omit, for example, all the processors other than the main unit processor, resulting in reduction of the hardware scale. If the emulation handler emulates processings of the processor in the input/output device, the reception/transmission circuit is not necessarily required.
The emulation handler may write at least one of an output buffer data presence flag, an input buffer data presence flag and an input/output device identification flag into the status register instead of at least one of the processors. The output buffer data presence flag, input buffer data presence flag and input/output device identification flag can be set without using the processors of the input/output controller and input/output device. Therefore, an appropriate emulation can be executed while reducing the hardware scale.
The emulation handler may write data for generating a second interrupt for the central control means into the port register instead of at least one of the processors. The second interrupt can be generated without using the processors of the input/output controller and input/output device, and can be used to execute various interrupt processings.
By making a signal of the first interrupt active for a given time period after the central control means executes an input/output instruction, the central control means may shift surely to a management mode activated by the first interrupt before executing a subsequent instruction. When the central control means executes an input/output instruction, the executed input/output instruction can be trapped so that the system can surely be shifted to the emulation processing.
The first interrupt may be a System Management Interrupt (SMI). By using SMI and activating the SMI signal for a given time period after the central control means has executed an input/output instruction, the central control means can surely shift to the System Management Mode (SMM) for performing the emulation before executing the next instruction.
The present invention further provides an information processing device including any one of the aforementioned emulation systems, wherein circuitry of the emulation system is formed on one chip together with other circuits of the information processing device. Since the area on which the input/output controller IC is mounted can be saved, resulting in a compact information processing device.
The present invention further provides an information processing device including any one of the aforementioned emulation systems, wherein a keyboard which is the input/output device is formed integrally with a main unit including the central control means. Particularly when emulating processings of a processor in the keyboard, the number of processors required by the information processing device can be reduced. Therefore, the size and cost of the information processing device can be reduced.
The present invention further provides a card-sized information processing device including any one of the aforementioned emulation systems, wherein at least the central control means and a memory are mounted on a card-sized board. This card type information processing device can emulate the input/output controller without using the hardware resource thereof. This can provide a card type information processing device of more compacted size.